The present invention generally relates to a packaging technique for a semiconductor integrated circuit, and more particularly to a packaging technique for a semiconductor integrated circuit employing a large-sized semiconductor substrate such as a semiconductor wafer.
In general, a semiconductor integrated circuit is constructed on a region, i.e., a semiconductor wafer chip, which is subdivided at the dicing regions after forming the semiconductor wafer. However, different researches have been recently made on the construction of a semiconductor integrated circuit where the semiconductor wafer is not subdivided, but a plurality of integrated circuits are fabricated on the entire semiconductor wafer so as to construct a large-sized semiconductor integrated circuit. Such a semiconductor manufacturing technique is described in, e.g., Japanese patent KOKAI (Disclosure) 61-290739, in which one large-sized semiconductor integrated circuit is constructed on the entire semiconductor wafer.
The present invention further relates to a semiconductor device, and more particularly to a useful technique applicable to a semiconductor device wherein a plurality of semiconductor chips are mounted on mounting substrates (module), and thereafter these mounting substrates are sealed by the same package.
To achieve higher package density of a semiconductor chip, a plurality of semiconductor chips are provided in a single package. Each of the semiconductor chips provided within the package is mounted on a mother chip. Aluminum wiring lines overlay the mother chip to interconnect the semiconductor chips. The aluminum wiring lines and the semiconductor chips are connected by bump electrodes made of gold (Au), solder and so on. For instance, the conventional semiconductor device where a plurality of semiconductor chips are mounted on a single package is described in Japanese patent KOKAI (Disclosure) application No. 60-198758.
The present invention further relates to a wafer-sized semiconductor integrated circuit device, and, for instance, to a useful technique for providing a wafer-sized semiconductor memory device.
A semiconductor memory device fabricated using a wafer-sized very large scale integrated circuit (VLSI) has been proposed in, for instance, Japanese patent KOKAI (Disclosure) application No. 59-201441. In the wafer-sized semiconductor memory device as described in the above application, cutting the failing chips and relieving these defective chips are performed in such a way that fuses, or power source lines, are cut out by irradiating focused ion beams, or laser light rays, and only the fault-free chips are connected by the final wiring.
Moreover, the present invention further relates to a method for manufacturing a packaging substrate, and, more particularly, to a useful technique applicable to a packaging substrate for packaging an LSI (large scale integrated circuit) chip.
A chip carrier type package, as a package suitable for higher packaging density of LSI, is known (known from, for instance, "VLSI Device Handbook", issued on Nov. 28, 1983, pages 226 to 228 by Science Forum). The so-called "alumina green sheet (non-sintered alumina sheet)" is most commonly utilized as the material of the packaging substrate employed for packaging the LSI in accordance with the above chip carrier method (for example, described on pages 239 to 242). When forming the packaging substrate by employing this green sheet, through holes are formed by way of photo-lithography and etching techniques which are commonly utilized for fabricating an LSI; thereafter, for instance, W-paste is printed to fill the through holes with the W-paste; and, finally, the green sheet is sintered.